1. Field of the Invention
The present disclosure generally relates to the field of fabrication of integrated circuits, and, more particularly, to manufacturing an interconnect structure requiring wet chemical cleaning processes of surfaces including exposed copper areas.
2. Description of the Related Art
In a complex integrated circuit, a very large number of circuit elements, such as transistors, capacitors, resistors and the like, are formed in or on an appropriate substrate, usually in a substantially planar configuration. Due to the large number of circuit elements and the required complex layout of the integrated circuits, generally the electrical connection of the individual circuit elements may not be established within the same level on which the circuit elements are manufactured, but requires one or more additional “wiring” layers, also referred to as metallization layers. These metallization layers generally include metal lines, providing the inner-level electrical connection, and also include a plurality of inter-level connections, also referred to as vias, wherein the metal lines and vias may also be commonly referred to as interconnect structures.
Due to the continuous shrinkage of the feature sizes of circuit elements in modern integrated circuits, the number of circuit elements for a given chip area, that is, the packing density, also increases, thereby requiring an even larger increase in the number of electrical interconnections to provide the desired circuit functionality. Therefore, the number of stacked metallization layers typically increases as the number of circuit elements per chip area becomes larger. Since the fabrication of a plurality of metallization layers entails extremely challenging issues to be solved, such as ensuring the mechanical, thermal and electrical reliability of many stacked metallization layers that are required, for example, for sophisticated microprocessors, semiconductor manufacturers are increasingly using a metal that allows for high current densities and reduced dimensions of the interconnections. For example, copper is a metal generally considered to be a viable candidate due to its superior characteristics in view of higher resistance against electromigration and significantly lower electrical resistivity when compared with other metals, such as aluminum, that have been used over the last decades. In spite of these advantages, copper also exhibits a number of disadvantages regarding the processing and handling of copper in a semiconductor facility. For instance, copper may not be efficiently applied onto a substrate in larger amounts by well-established deposition methods, such as chemical vapor deposition (CVD), and also may not be effectively patterned by the usually employed anisotropic etch procedures due to its lack of forming volatile etch byproducts. In manufacturing metallization layers including copper, the so-called damascene technique is therefore preferably used wherein a dielectric layer is first applied and then patterned to receive trenches and vias, which are subsequently filled with copper. A further major drawback of copper is its property to readily diffuse in low-k dielectric materials, silicon and silicon dioxide, which is a well-established and approved dielectric material in fabricating integrated circuits.
It is therefore necessary to employ a so-called barrier material in combination with a copper-based metallization to substantially avoid any out-diffusion of copper into the surrounding dielectric material, as copper may readily migrate to sensitive semiconductor areas, thereby significantly changing the characteristics thereof. On the other hand, the barrier material may suppress the diffusion of reactive components into the metal region. The barrier material provided between the copper and the dielectric material should exhibit, however, in addition to the required barrier characteristics, good adhesion to the dielectric material as well as to the copper and should also have as low an electrical resistance as possible so as to not unduly compromise the electrical properties of the interconnect structure. Moreover, the barrier layer may also act as a “template” for the subsequent deposition of the copper material in view of generating a desired crystalline configuration, since a certain degree of information of the texture of the barrier layer may be transferred into the copper material to obtain a desired grain size and configuration. It turns out, however, that a single material may not readily meet the requirements imposed on a desired barrier material. Hence, a mixture of materials may frequently be used to provide the desired barrier characteristics. For instance, a bi-layer comprised of tantalum and tantalum nitride is often used as a barrier material in combination with a copper damascene metallization layer. Tantalum, which effectively blocks copper atoms from diffusing into an adjacent material, even when provided in extremely thin layers, however, exhibits only a poor adhesion to a plurality of dielectric materials, such as silicon dioxide based dielectrics, so that a copper interconnection including a tantalum barrier layer may suffer from reduced mechanical stability, especially during the chemical mechanical polishing of the metallization layer, which may be employed for removing excess copper and planarizing the surface for the provision of a further metallization layer. The reduced mechanical stability during the CMP process may, however, entail severe reliability concerns in view of reduced thermal and electrical conductivity of the inter-connections. On the other hand, tantalum nitride exhibits excellent adhesion to silicon dioxide based dielectrics, but has very poor adhesion to copper. Consequently, in advanced integrated circuits having a copper-based metallization, typically a barrier bi-layer of tantalum nitride/tantalum is used. The demand for a low resistance of the interconnect structure in combination with the continuous reduction of the dimensions of the circuit elements and associated therewith of the metal lines and vias requires the thickness of the barrier layer to be reduced, while nevertheless providing the required barrier effect. It has been recognized that tantalum nitride provides excellent barrier characteristics even if applied with a thickness of only a few nanometers and even less. Thus, sophisticated deposition techniques have been developed for forming thin tantalum nitride layers with high conformality even in high aspect ratio openings, such as the vias of advanced metallization structures, wherein the desired surface texture with respect to the further processing may also be obtained.
Since the dimensions of the trenches and vias have currently reached a width or a diameter of approximately 0.1 μm and even less with an aspect ratio of the vias of about 5 or more, the deposition of a barrier layer reliably on all surfaces of the vias and trenches and subsequent filling thereof with copper substantially without voids is a very challenging issue in the fabrication of modem integrated circuits. Currently, the formation of a copper-based metallization layer is accomplished by patterning an appropriate dielectric layer to form trenches and/or vias therein and depositing the barrier layer, for example comprised of tantalum (Ta) and/or tantalum nitride (TaN), by advanced physical vapor deposition (PVD) techniques, such as sputter deposition. Due to the many constraints for advanced devices, as explained above, the surface of the patterned structure may have to be conditioned prior to the deposition of the barrier material and also prior to the deposition of the copper material. For this purpose, usually wet chemical cleaning processes may be performed, for instance, on the basis of hydrofluoric acid. Thereafter, the copper is filled in the vias and trenches, wherein electroplating has proven to be a viable process technique, since it is capable of filling the vias and trenches with a high deposition rate, compared to CVD and PVD rates, in a so-called bottom-up regime, in which the openings are filled starting at the bottom in a substantially void-free manner.
It turns out, however, that in higher metallization levels a degradation of the vias may be observed, which is believed to be caused by tiny copper voids at the interface of a via to an underlying copper line. These voids in the copper interface may be created during the patterning of the overlying dielectric material of the next metallization layer, since, in this sequence, copper of the lower copper line is exposed within the via opening formed in the overlying dielectric material. Thus, at a certain state, after etching respective trenches for the metal lines of the next metallization layer, copper in the associated vias may be exposed, thereby resulting in copper voids and thus interconnect degradation.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.